The present invention relates generally to driver circuits and methods of operating them and, more particularly, to a driver circuit including first and second opposite conductivity type transistors which are prevented from conducting simultaneously in response to a transition between first and second voltage levels of a bilevel source by circuitry including a switched capacitor.
One type of driver circuit that is frequently employed, particularly on integrated circuit chips, includes first and second opposite conductivity type transistors, each including a control electrode and a path which is switched on and off between a pair of further electrodes. Each path is switched on and off in response to a voltage applied to the control electrode of the particular transistor being on opposite sides of a threshold. The paths of the first and second transistors are connected in series across terminals of a DC power supply. An output terminal between the series connected paths drives a load.
In a typical integrated circuit chip, the transistors are opposite conductivity type metal oxide semiconductor field effect transistors (MOSFETs), wherein the control electrodes are gate electrodes and the further electrodes are source and drain electrodes. Such a driver includes a positive channel field effect transistor (PFET) and a negative channel field effect transistor (NFET). The switched path between the source and drain electrodes of each field effect transistor (FET) is frequently referred to as a source drain path and the source drain paths of the PFET and NFET are connected in series across opposite polarity terminals of the power supply.
The typical integrated circuit chip includes many such drivers that are responsive to bilevel sources having positive and negative going transitions between first and second voltage levels that are usually approximately equal to the voltages at the power supply terminals. The bilevel sources can be either data or clock sources. In response to the bilevel source being at the first (low) voltage level, the PFET and NFET are respectively on and off, while the NFET and PFET are respectively on and off in response to the bilevel source being at the second (high) voltage level. A relatively high impedance is provided by the source drain path of the NFET or PFET which is off so that substantial current does not flow through both the PFET and NFET of the driver while the bilevel source is at the first and second voltage levels. To minimize power consumption, the PFET and NFET should not be on at the same time during the transitions.
Many of the drivers of the foregoing type on a typical integrated circuit chip are simultaneously responsive to the transitions. If many of the drivers of the foregoing type are simultaneously responsive to the transitions and if the PFET and NFET of each of these drivers were on at the same time during the transitions, a substantial amount of current, frequently referred to as crow bar current would be drawn from the power supply. The current could be so great as to cause overheating of the integrated circuit chip and result in a substantial decrease in the voltage between the power supply terminals. Similar problems can also exist with bipolar drivers including PNP and NPN transistors having series connected emitter collector paths.
In the past, one approach to resolving the problem has involved complicated circuitry which takes into account processing variables in making the integrated circuits, as well as changes that occur to the circuit elements as a result of power supply voltage and temperature variations of the integrated circuit chip carrying the circuitry. Another complicated approach has involved staging a number of field effect transistors. These complicated circuits occupy a significant amount of space on the integrated circuit chip and consume additional power, resulting in possible unnecessary heating of the chip.
There is a prior art circuit wherein conventional capacitors are connected in negative feedback paths to the gate electrodes of opposite conductivity type field effect transistors having series connected source drain paths. A problem with using conventional capacitors is that the slope of the exponential waveform which results in response to a transition being applied to such capacitors decreases substantially as the voltage across the capacitor approaches a target value associated with the DC power supply voltage. Consequently, the use of conventional capacitors is usually incompatible with high frequency operation, such as is associated with integrated circuits operating in excess of a few hundred MHz. In this prior art circuit, both field effect transistors appear to be turned on simultaneously during a transition, resulting in substantial current flow. Another problem with this prior art circuit is that the capacitors are charged and discharged through source drain paths of additional field effect transistors, rather than through resistors.
In accordance with one aspect of the present invention, a driver circuit comprises an input terminal for connection to a voltage source having first and second levels and a transition between the levels. The driver circuit includes first and second opposite conductivity type transistors, each including a control electrode and a path which is switched on and off between a pair of further electrodes in response to a voltage applied to the control electrode being on opposite sides of a threshold. The paths of the first and second transistors are connected in series across opposite power supply terminals. Circuitry connected between the first terminal and the control electrodes causes the paths of the first and second transistors to be (1) respectively on and off while the voltage source has the first level, and (2) respectively off and on while the voltage source has the second level. At least one switched capacitor connected between the first terminal and the driver prevents the paths of the first and second transistors from being on simultaneously in response to transitions between the first and second levels.
Preferably, the at least one capacitor includes first and second voltage controlled switched capacitors respectively connected to delay coupling of the transitions to the control electrodes of the first and second transistors.
In the preferred embodiment, the first and second opposite conductivity type transistors are opposite conductivity type field effect transistors, that is, a PFET and NFET. In this embodiment, the first and second capacitors are preferably third and fourth field effect transistors having opposite conductivity types from the conductivity types of the first and second transistors, respectively. The gate electrodes of the first and third transistors are connected to each other, and the gate electrodes of the second and fourth transistors are connected to each other. The source drain path of the third transistor is connected to one power supply terminal, while the source drain path of the fourth transistor is connected to the other power supply terminal.
Preferably, the first and second capacitors are charged and discharged by first and second inverter circuits connected to be responsive to the voltage source. Each of the inverter circuits includes a pair of opposite conductivity type transistors each including a control electrode and a path which is switched on and off between a pair of further electrodes in response to the voltage which is applied to the control electrodes being on opposite sides of a threshold. The paths of the transistors of each inverter are connected in series across opposite power supply terminals. Each inverter includes a resistive impedance connected in the paths of the transistors of the particular inverter. The inverters and the resistive impedances thereof are connected so that (1) current flows through the resistive impedance of the first inverter and no current flows through the resistive impedance of the second inverter while the voltage of the source has the first level, and (2) current flows through the resistive impedance of the second inverter and no current flows through the resistive impedance of the first inverter while the voltage of the source has the second level. The foregoing arrangement provides excellent control for switching of the first and second transistors, while minimizing the power requirements of the circuitry.
In the preferred embodiment, wherein the driver circuit is on an integrated circuit chip, the first and second opposite conductivity type transistors are opposite conductivity type field effect transistors, that is, a PFET and NFET and the inverters also preferably include opposite conductivity type field effect transistors (FETs). Preferably, the resistive impedance on the integrated circuit chip is a resistor having a relatively low value that usually cannot be achieved by the source drain impedance of a FET. The low value of the resistor is desirable for high frequency uses because it provides a relatively short delay time. A resistor also has the advantage over a FET source drain path because the resistive impedance of a resistor is not subject to the extensive variations in value as a function of chip processing, voltage and temperature that accompany a source drain path.
Another aspect of the invention is concerned with a method of operating a driver including first and second opposite conductivity type transistors, each including a control electrode and a path between a pair of further electrodes controlled in response to a voltage applied to the control electrode. The paths of the first and second transistors are connected in series across opposite power supply terminals. There is an output terminal between the series connected paths. First and second switched capacitors are respectively connected in shunt with the control electrodes. The method comprises during a first interval: turning on and off the paths of the first and second transistors, respectively, while the second capacitor is charged and the first capacitor is switched off by applying (1) a first voltage having a first value to the control electrode of the first transistor, (2) the first voltage value across the second capacitor, and (3) a second voltage having the first value to the control electrode of the second transistor. During a second interval, the first and second transistors are turned off and on, respectively, while the second capacitor is switched off and the first capacitor is charged by applying (1) the second value of the first voltage to the control electrode of the first transistor, (2) the first voltage value across the first capacitor, and (3) the second value of the second voltage to the control electrode of the second transistor. During an initial portion of a first transitional period between the first and second intervals, the path of the first transistor is turned off while the path of the second transistor is maintained off by changing the first voltage from the first value toward the second value while the first capacitor remains turned off and the second capacitor is charged. During a second portion of the first transitional period, the path of the second transistor is turned on while the path of the first transistor is maintained off by changing the charge on the second capacitor so that there is a change in the value of the second voltage from the first value toward the second value. During an initial portion of a second transitional period between the second and first intervals, the path of the second transistor is turned off while the path of the first transistor is maintained off by changing the second voltage from the second value toward the first value while the second capacitor remains turned off and the first capacitor is charged. During a second portion of the second transitional period the path of the first transistor is turned on while the path of the second transistor is maintained off by changing the charge on the first capacitor so that there is a change in the value of the first voltage from the second value toward the first value.
In the preferred embodiment, the first capacitor is switched off during the second portion of the first transitional period prior to the value of the first voltage, as applied to the control electrode of the first transistor, reaching the first value, and the second capacitor is switched off during the second portion of the second transitional period prior to the value of the second voltage, as applied to the control electrode of the first transistor, reaching the second value. The first and second capacitors are preferably switched on and off in response to the first and second voltages having values on opposite sides of first and second thresholds respectively associated with the first and second capacitors.
The above and still further objects, features and advantages of the present invention will become apparent upon consideration of the following detailed description of a specific embodiment thereof, especially when taken in conjunction with the accompanying drawings.